Method and apparatus for designing an integrated circuit using inverse lithography technology

ABSTRACT

Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.

CROSS-REFERENCE TO RELATED APPLICATIONS(S)

This application is a national phase entry under 35 U.S.C. §371 ofInternational Application No. PCT/IB2006/003053 filed 16 Aug. 2006.

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for designing anintegrated circuit.

BACKGROUND OF THE INVENTION

When making an integrated circuit (which may also be referred to as anIC, chip or device), a design layout of the IC is made using, forexample, CAD tools. A reticle or mask is then produced for the IC designlayout and then photolithography is used to transfer features from thereticle or mask to a die (integrated circuit semiconductor wafer).

Various techniques are used to reduce the level of defects in theresultant die. Significant causes of defects are due to optical effects(especially diffraction) which distort the image of the reticle on thesemiconductor wafer. Resolution enhancement technologies (RET) are usedto limit this distortion. However, as the scale of features on an ICreduces so the impact of optical effects increases.

In one particular RET, prior to the production of the reticle, thedesign layout may be optimised using optical proximity correction (OPC)to create an optimised reticle layout as described in U.S. Pat. No.5,705,301.

Typically, the OPC process involves identification of features thatrequire optimisation. For instance, a rule based approach may be used tofind features exhibiting particular properties, e.g. properties that mayresult in defects when the feature is transferred to the IC wafer. Thedistortion of features caused by the subsequent manufacturing process,including optical effects may be simulated by the OPC procedure. Thiscould include simulating the optical distortions and diffraction effectsoccurring when transferring the IC layout design on to an IC wafer.Defects may be identified in the IC layout design should the simulatedresult fall outside any predetermined tolerances or fail comparison withany other particular criteria. This identification of features requiringoptimisation shall be referred to as OPC simulation and may include therule based tests and/or the manufacturing simulation steps, which aretypically performed in OPC processes.

After OPC simulation any features containing defects may be optimised inorder to ensure that defects are removed or their effects minimised. Asdiscussed in U.S. Pat. No. 5,705,301 the OPC optimisation stage may usevarious techniques and amends the physical design layout in order toavoid optical or process distortions, also known as patterning defects,when features are transferred from the reticle or mask that may causefailures of the final device. Where distortions are found that arelikely to cause failures the OPC optimisation process discretizes thedesign layout into moveable segments and manipulates these segmentsuntil the distortions are minimised so that the risk of failures in theresultant chip is reduced.

The success of the optimisation of a particular feature may be tested bya further OPC simulation step and the process may iterate until thedefects are corrected or minimised.

The OPC procedure may take several iterations and is time consuming andtherefore, costly. However, as the critical dimension (CD) of featuresincorporated into IC designs decreases OPC optimisation must use rulesand models of increasing sophistication requiring ever more powerfulcomputer facilities and longer run times to implement.

One alternative RET is known as inverse lithography technology (ILT) orinverse OPC. Such an approach is described in “Inverse LithographyTechnology Principles in Practice: Unintuitive Patterns”, Yong Liu, DanAbrams, Linyong Pang and Andrew Moore, J. Proc. SPIE Vol. 5992, pp886-893 (2005). Inverse OPC uses a model of the optical system used totransfer the IC design layout onto a semiconductor wafer to create areticle layout that should form a pattern on the wafer closely matchingthe layout of the IC layout design itself. In effect, a goal is definedas being the undistorted image and the system is left to run until apattern is found that would pass through the modelled optical systemresulting in a desired image corresponding to the IC design layout orvery close to it. Inverse OPC is a highly parallel process whichconsiders large sections of the IC layout design at once.

Inverse OPC can result in reticle layouts that will very accuratelyproduce dies that closely match the required IC layout design. However,inverse OPC can only be used for optimising for optical effects and doesnot accurately consider other effects such as resist effects, forinstance. One major drawback with inverse OPC is that the reticle designthat is generated by inverse OPC cannot usually be manufacturedsuccessfully due to the complexity or fine structure of the generatedreticle designs.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for designing anintegrated circuit as described in the accompanying claims.

BRIEF DESCRIPTION OF THE FIGURES

The present invention may be put into practice in a number of ways andan embodiment will now be described by way of example only and withreference to the accompanying drawings, in which:

FIG. 1 shows a flowchart of a method for designing an integrated circuitaccording to an embodiment of the present invention; and

FIG. 2 shows a reticle layout design generated by an embodiment of thepresent invention, given by way of example.

It should be noted that the figures are illustrated for simplicity andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF AN EMBODIMENT

FIG. 1 shows a flowchart 10 showing the steps for designing an IC. An IClayout design together with a model describing an optical system used totransfer the IC layout design onto a semiconductor wafer is used tocalculate an ideal reticle layout design. This process uses a suitableinverse OPC procedure 20 such as one described in J. Proc. SPIE Vol.5992, pp 886-893 (2005) mentioned previously. The resulting idealreticle layout design is analysed to located the boundaries of itsfeatures 30. Typically, the features contain details that cannot bemanufactured because, for instance, they are too complex or too small.Once the boundaries of the features are found nodes or peaks in theboundaries are located 40. Then, these located nodes are replaced orapproximated 50 with segments that are similar in size and/or shape tosegments added to an IC layout design during an OPC procedure. Thissimplifies the reticle layout design. In particular, these segmentsshould be manufacturable on a reticle and subsequent IC wafer.

The simplified reticle layout design may be used as the starting pointfor an OPC procedure 60. This OPC procedure 60 may be OPC simulation orOPC optimisation or both. The nodes located on the boundaries of thefeatures become the segments used to optimise features within the IClayout design when the OPC procedure is executed. In this way the OPCprocedure does not need to generate all required segments but hasinstead a more advanced starting point having segments in at leastapproximated positions. A reticle may then be manufactured and used tocreate a semiconductor die.

FIG. 2 shows a reticle layout design 100 formed during various steps ofthe method described with reference to FIG. 1.

Line 110 defines the boundary of a feature of the reticle layout designafter the inverse OPC procedure 20 has completed and can be seen ascomprising a plurality of small discrete steps. The finest features,i.e. the steps of this boundary may be too small to be reliablymanufactured.

Line 120 defines the theoretical structure of a wafer die that could beformed from a reticle having the structure defined by line 110 shouldsuch a reticle be manufacturable. The form of line 120 is calculatedduring the inverse OPC procedure. However, this theoretical structureonly takes into account optical effects. Obviously, this calculation istheoretical as it is unlikely that such a reticle could be manufacturedusing current technology due to the complex nature of the requiredreticle layout and the small steps that make up line 110.

Nodes 140 of line 110 are identified by one or more of severaltechniques such as using the maximum local difference between thetheoretical structure and the initial design layout as the centre of anode, or using the points on the theoretical structure with highestlocal slope as the endpoints of a node. The nodes 140 are approximatedand replaced with simpler segments 150 having lower complexity comparedwith line 110. This results in the simplified structure shown as line130. For instance, the segments 150 may be simple rectangular shapeswhich are parallel to the initial design layout, whereas the nodes 140comprise more complex shapes having more edges.

Although line 130 defines a simplified structure at least some of thebenefits of the inverse OPC procedure are retained leading to a waferdie having a structure closer to the ideal yet being formed from amanufacturable reticle having fewer angled edges. These benefits may notbe possible from carrying out an OPC procedure alone and may include thegeneration of unintuitive structures that cannot be generated fromeither a rule based or model based OPC procedure.

As described with regards to FIG. 1, the simplified structure defined byline 130 may be used as the input to an OPC procedure in order tofurther reduce the risk of defects occurring on the resultant wafer die.When OPC is carried out alone using the initial IC layout design as astarting point the preferred locations of the moveable segments isunknown. Consequently, several iterations may be required before thepreferred or optimum locations are found or an acceptably accuratelocation may not be found. Performing the method described with regardsto FIG. 1 prior to performing OPC, provides the OPC procedure with amore accurate initial estimate as to the optimum locations of thesegments and so may reduce the risk of defects and reduce the number ofiterations required and therefore, the total execution time.

Furthermore, the rules or models used by the OPC procedure may belimited to those used to correct for non-optical effects with the bulkof the work already carried out by the inverse OPC procedure. Also,inverse OPC is better suited than OPC to correct for opticalinterference effects with higher coherence light sources which causewaviness or ringing in the resulting wafer pattern. To compensate foroptical interference effects requires high accuracy placement of themoveable segments in the mask layout. Inverse OPC automaticallycalculates the optimum mask layout to correct for these interferenceeffects. Traditional iterative OPC is not capable of this as the optimumposition for a moveable segment changes at each iteration.

It may be advantageous to restrict the resources required to design andtest the IC layout design. For instance, certain regions of the IClayout design may consist of lower complexity features that are lesslikely to contain defects. This may also be the case where complexfeatures are repeated many times so that if any potential defects arenot removed there is a higher risk that defects will be found in thedevice.

In a further embodiment of the method of the present invention themethod 10 described above is carried out on particular individualregions of a IC layout design and the remaining regions are excludedfrom this treatment. The particular individual regions chosen may dependon several factors. For instance, lower complexity regions such as thosededicated for logic functions (and so containing few repeatedstructures) may be ignored. Higher complexity regions such as thosededicated to memory functions (and so containing many repeatedstructures) may be subjected to the method 10 described above. Featurecomplexity can be calculated using measurements of minimum featuredimensions, using counts of feature vertices or other geometric methods.

Alternative ways of determining which regions to treat in this wayinclude defining regions during the design stage (either manually orautomatically), or applying other rule based criteria such asdetermining the feature density of each region and excluding lowerdensity regions from further treatment.

As a further alternative certain aspects of the method 10 describedabove may be excluded from particular regions of the IC layout designrather than excluding the entire method. For instance, the inverse OPCstep may be included but the OPC procedure 60 (including simulationand/or optimisation steps) may be excluded.

The method described above may be carried out in an automated mannerusing suitable apparatus or a computer programmed to perform each of themethod steps.

As will be appreciated by the skilled person, details of the aboveembodiment may be varied without departing from the scope of the presentinvention, as defined by the appended claims.

For example, the nodes of the border defined by line 110 may be found bysimulated image light intensity maxima, minima or gradient calculationsto identify the major positive and negative modulations of the imagesuch as are commonly performed in signal processing or opticalengineering applications.

It will be appreciated that the additional embodiment of excludingcertain regions from further analysis based on each regions' complexityis not restricted to the method 10 described above. For instance, otherforms of defect identification or optimisation methods may be restrictedto particular regions based on complexity or structure in a similar way.

1. A method of designing an integrated circuit, IC, comprising the stepsof: performing inverse optical proximity correction (OPC), using acomputer, to generate an optimized reticle layout design from an IClayout design and a model describing an optical system for transferringthe IC layout design onto a semiconductor wafer using a reticle, whereinthe optimized reticle layout design comprises features defined by aplurality of boundaries; approximating the plurality of boundaries togenerate an approximated reticle layout design suitable for themanufacture of the IC; and performing OPC simulation on at least aportion of the approximated reticle layout design in order to identifyfeature defects.
 2. The method of claim 1, wherein the approximatingstep further comprises the step of: identifying nodes in the pluralityof boundaries.
 3. The method of claim 2, wherein the approximating stepfurther comprises the steps of: replacing each node with a discretesegment.
 4. The method of claim 3 further comprising the step ofperforming OPC optimization using the approximated IC layout design. 5.The method of claim 2, wherein the nodes are identified by applying alow-pass filter to the optimized reticle layout design.
 6. The method ofclaim 5 further comprising the step of performing OPC optimization usingthe approximated IC layout design.
 7. The method of claim 2, wherein thenodes are identified by measuring the gradient along each boundary suchthat a specified change in gradient indicates the presence of a node. 8.The method of claim 2 further comprising the step of performing OPCoptimization using the approximated IC layout design.
 9. The method ofclaim 1 further comprising the step of flagging the identified featuredefects for later investigation.
 10. The method of claim 9 furthercomprising the step of performing OPC optimization using theapproximated IC layout design.
 11. The method of claim 1 furthercomprising the step of performing OPC optimization using theapproximated IC layout design.
 12. The method of claim 1, furthercomprising the steps of: identifying regions in the IC layout designhaving different degrees of complexity; and performing the method stepsof claim 1 on regions having a particular degree of complexity.
 13. Themethod according to claim 12, wherein the particular degree ofcomplexity falls within a range of complexity.
 14. The method accordingto claim 13, wherein the regions having different degrees of complexityrelate to memory functions and/or logic functions.
 15. The methodaccording to claim 13, wherein the identifying step further comprisesdetermining the feature density of the IC layout design.
 16. The methodaccording to claim 12, wherein the regions having different degrees ofcomplexity relate to memory functions and/or logic functions.
 17. Themethod according to claim 16, wherein the identifying step furthercomprises determining the feature density of the IC layout design. 18.The method according to claim 12, wherein the identifying step furthercomprises determining the feature density of the IC layout design. 19.An apparatus for designing an integrated circuit comprising: means forperforming inverse optical proximity correction (OPC) to generate anoptimized reticle layout design from an IC layout design; a modeldescribing an optical system for transferring the IC layout design ontoa semiconductor wafer using a reticle, wherein the optimized reticlelayout design comprises features defined by a plurality of boundaries;means for approximating the plurality of boundaries to generate anapproximated reticle layout design suitable for the manufacture of theIC; and means for performing OPC simulation on at least a portion of theapproximated reticle layout design.